Finally, a company shows you can have a high performance RISC-V solution with RAS capabilities

I will be honest with you. For years I didn’t quite understand all the attention the RISC-V ecosystem or the solutions were getting. I’ve seen very small CPU cores used without high-level operating systems in standalone environments. These replaced the Arm M0 solutions in hard disk controllers. There’s value in that, but it’s just not the sort of thing that I think is game-changing in the industry.

Also, from a business model perspective, you still had to pay someone to design the RISC-V chip, so why bother paying either the designer or Arm? There are no free meals. The other thing that was a bit annoying was that I didn’t see any solutions with a lot of compute power or RAS features that would make a difference in the data center market. CPU performance hard disk controller type. Yes, I recognized ISA extensibility at accelerators, but it appeared that Arm plugged that hole and it might cause ISA “compatibility” issues down the line.

Then Ventana Systems came on the scene.

Over the past six months, the company has let me in on some details of its plans that sound pretty compelling. This week at the RISC-V summit, the company officially announced what had been hidden for years – Veyron, which the company calls “the world’s first data center-class RISC-V processor”. He gave details of Veyron V1 and showed that a year later we would see a V2.

It’s more than a slideshow. I think the company has major design commitments spanning the data center to the edge that could be in live systems by the end of 2023.

So what are the chiplet, processor or IP capabilities of the Veyron V1 processor?

• Eight large aggressive out-of-order instruction pipelines
• 3.6GHz
• 5nm process technology
• 16 cores per cluster
• High core count multi-cluster scalability (up to 192 cores)
• 48MB shared L3 cache
• Advanced Side Channel Attack Mitigation
• IOMMU and Advanced Interrupt Architecture (AIA)
• Full compliance with RVA22 application profile
• System-level code profiling

What strikes me about this bulleted list is that it is designed for high performance, RAS (Reliability, Serviceability. Availability) and security. Higher levels of RAS and security are required in the data center, data center edge, carrier use cases, and in the software-defined vehicle.

The company is committed to delivering the best single thread and socket performance over other RISC-V designs. From what I understand, it will be, at the beginning, an easy bar to cross. No one else, to my knowledge, is that far. The performance bar over the next two years is for the Arm and X86 ISAs and Ventana hasn’t been shy about showing that it outperforms current processors like Xeon Ice Lake, EPYC Milan (Zen 3) and AWS Graviton 3 with those that will be at the end of 2023.

Simple math indicates that Ventana should improve future performance with V2 to beat upcoming chips and IPs from Arm, Intel, AMD, and AWS, but that may miss the point. ventana no have to beat everyone, you just have to be in the respectable range, which, if the company keeps its promises, it will. We can’t forget that the magic of a RISC-V based CPU isn’t just the performance, it’s the custom instructions and accelerators that can be used.

While I had previously dismissed the “extensible ISA” capabilities inherent in the RISC-V architecture as messy and Arm-reproducible, the Ventana design wins all of that. The company has built a network of partners around it with solutions for storage, AI, 5G acceleration, etc. What I need to do more research on is the degree of software compatibility when we get many different flavors of RISC-V processors on the market.

It’s also worth noting that Ventana targets the same places that the early Arm-based implementations targeted and succeeded with. These are workloads such as web hosting, in-memory databases, storage, load balancing, caching, CDN, and streaming. This comes straight from the Arm playbook because…. it works, and many Ventana employees came from Arm-based data center processing companies. None of this should come as a surprise.

Let’s talk software. This one is tricky. If there’s one question I hear the most about how successful RISC-V is in higher-order use cases, it’s software. I understand. We’ve all watched the 10+ years it took to create the Arm stack for the data center. I’m not ready to declare “success” or “done” on this. Here is what I know:

• Arm paved the way for the most popular non-x86 tools, firmware, BIOS, operating system and use cases with open source software
• Cloud giants have their own software stacks and have the resources to move mountains
• these people have learned the ins and outs of non-X86 and seem to be taking those skills to RISC-V faster with the direction of Ventana
• the logic indicates that the RISC-V time will be shorter than the arming time

Ultimately, I’ll be more convinced by real companies running real production workloads. I think Ventana knows exactly what he’s getting into because he was at the center of the Arm software battle.

Summary

I previously didn’t see RISC-V as a viable alternative in data-centric environments because I witnessed the pain that Arm and its partners went through and didn’t see enough differentiation that people change. Enter Ventana.

However, I can’t question the design wins, and I think Ventana has plenty of those. The reasons they want to use Ventana are:

• enough performance today and confidence in future performance
• expandable ISA acceleration capabilities
• experienced leadership that has gone through the x86 crucible and Arm
• go-to-market flexibility with full IP, core and processor

The two founders of Ventana, Balaji Baktha and Greg Favor, have already been through fire with the x86 and Arm wars. I believe both have very few blind spots on what the business needs to do to gain a foothold. If there’s one team that I think can do it in the RISC-V space, I believe it’s this one. Baktha and Favor can’t change the degree of competitive response, but the company can execute what looks like a good plan just fine. I can’t wait to see what the future holds for the Veyron 1 and 2.

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