The info created and transferred between billions of gadgets and the cloud is rising exponentially. Increasingly gadgets are coming to market, the cloud is increasing to the community edge, and new purposes are rising. These elements are driving technological developments in excessive efficiency computing (HPC), redesigning of system-on-chip (SoC) designs to satisfy the necessity for acceleration, storage capability, new compute architectures and tapes. elevated bandwidth for sooner knowledge motion.

As expertise revolutionizes and knowledge will increase, knowledge and system safety is paramount. With poor safety mechanisms, attackers may search to reap the benefits of secret info and intrude with the lives of personal residents or the operations of enterprise and authorities. A number of elements are propelling these safety wants: enhance in confidential and delicate info, legal guidelines and laws, altering nature of safety threats, and evolving requirements.

Safety options should help the bandwidth of the newest interfaces, low latency necessities, and minimal space, whether or not defending knowledge in transit or knowledge at relaxation.

Reminiscence and storage safety includes defending storage assets and knowledge saved on-premises, in exterior knowledge facilities, and within the cloud.

To guard knowledge, designers are turning to high-performance, low-latency reminiscence encryption options that protect efficiency whereas securing knowledge over the newest generations of reminiscence interfaces.

The AES-XTS cryptographic algorithm is on the coronary heart of reminiscence safety

AES-XTS, or as it’s generally known as XTS-AES, is the de facto cryptographic algorithm for safeguarding the confidentiality of information at relaxation on storage gadgets. It’s a symmetric, standards-based algorithm outlined by NIST SP800-38E and IEEE Std 1619-2018 specs that, by its nature, allows pipelined architectures whose efficiency can scale as much as bandwidth terabits per second (Tbps). Ciphertext theft (CTS) mode helps knowledge models whose dimension just isn’t divisible by the 16-byte block dimension of the underlying AES cipher.

AES-XTS is the important element for reminiscence safety in HPC purposes. It ought to be extremely optimized and scaled to help elevated bandwidths whereas conserving latency and space as little as potential and enabling seamless SoC bodily design and time gate. Along with being absolutely compliant with cryptographic specs, AES-XTS options should help encryption and decryption for all key sizes, allow clear context switching for numerous contexts, help configuration /efficient key refresh and be certifiable, eg. for instance, to FIPS 140-3 Degree 2 necessities as a typical goal, or Degree 3 for extra delicate purposes.

Extremely Excessive Efficiency AES-XTS IP for HPC

When searching for storage or reminiscence encryption IP options for HPC SoCs, it’s important to think about optimized options from trusted IP distributors that ship the best efficiency, lowest latency, and optimum space, conform to the newest requirements and are backed by specialists.

Additionally it is essential that the mental property is constructed via a rigorous safety improvement course of that features:

  • Establish applicable property akin to plaintext, ciphertext, cryptographic keys and state, and key utilization coverage
  • Outline safety aims to guard these property, guaranteeing that the plaintext obtained on the core ingress can’t be accessed via different interface ports and solely the related ciphertext is transmitted from the port Launch ; keep the confidentiality of cryptographic keys; and lots of others
  • Implement applicable safety mechanisms and supply pointers for SoC integrators to realize safe integration of their designs.

Synopsys’ ultra-high efficiency AES-XTS cryptographic IP core (Determine 1) solves these issues whereas offering the configurability wanted to adapt to particular use instances and efficiency necessities of SoC designs.

By integrating Synopsys’ standards-compliant AES-XTS encryption cores, HPC SoCs profit from:

  • Excessive-performance, low-latency IP with environment friendly help for diverse knowledge visitors
  • Scalable throughput from 128 to 4096 bits/cycle, reaching bandwidths past 4 Tbps
  • Environment friendly encryption and decryption with 256-bit and 512-bit AES-XTS key sizes
  • Latency as little as 4 cycles
  • An adjustment by cycle precalculation
  • Clear message interleaving, key configuration, and key refresh for as much as 64,000 cryptographic contexts
  • Multi-clock area help
  • Devoted safe key port
  • Space, latency, efficiency and max frequency optimization choices
  • FIPS 140-3 certification prepared
  • Path for seamless integration of full-duplex inline reminiscence encryption with reminiscence interface controllers, together with the newest era DDR4/LPDDR4, DDR5/LPDDR5, and HBM

With Synopsys’ ultra-high efficiency AES-XTS IP, designers can be certain that the reminiscence safety of their HPC SoCs is strong and the confidentiality of information at relaxation is maintained even within the face of recent threats.

Fig. 1: Synopsys Extremely Excessive-Efficiency AES-XTS Crypto IP block diagram.


With the large progress of information and bandwidth in our related world, safety is crucial to guard personal and delicate knowledge because it strikes between methods to storage, together with reminiscence. On the coronary heart of storage safety is the AES-XTS cryptographic algorithm, which should help scalable excessive knowledge charges with minimal latency and space affect for HPC purposes.

Synopsys Extremely Excessive-Efficiency AES-XTS Crypto IP Cores meet the wants of the newest technological developments and safety necessities with superior options and capabilities whereas permitting them to be optimally configured for the particular use instances of the SoC designs.

Synopsys is uniquely positioned available in the market with complete standards-compliant safe interface options that align with the newest utility calls for and permit designers to rapidly implement the required safety on their SoCs with low danger and a quick time to market.

Along with ultra-high efficiency AES-XTS cryptographic cores for reminiscence encryption, Synopsys supplies a broad portfolio starting from standalone cryptographic cores to extremely built-in safety IP options that use a typical set of constructing blocks and safety ideas based mostly on requirements to allow essentially the most environment friendly silicon design and the best ranges of safety for a spread of merchandise within the cloud computing, cell, automotive, digital house and IoT markets.

For extra info, go to Synopsys IP Cryptography.

Dana Neustadter

Dana Neustadter

(All posts)

Dana Neustadter is Product Advertising Supervisor for IP Safety at Synopsys. She holds an M.Eng. and B. Sc. in Electrical Engineering from the Technical College of Cluj-Napoca.

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